AMD’s Next-Gen Carrizo APU Features Leaked, Shows Greater Focus On Power Efficiency

AMD’s Next-Gen Carrizo APU Features Leaked, Shows Greater Focus On Power Efficiency

We’ve discussed AMD’s next-generation Carrizo several times, most recently in the context of our deep dive into Steamroller’s performance. Now, new documents have surfaced that point to several of the APUs new features, its power efficiency improvements, and a few compromises AMD may have made to get there. Keep in mind that even if this information is accurate, it’s early and quite possibly incomplete.

Marcus Pollice of BSN has the scoop on this front thanks to a peek at the “Preliminary BIOS and Kernel Optimization Guide for AMD Family 15h Models 60h-6Fh Processors.” That naming convention fits AMD’s previous products and optimization guides. So what’s coming in the new chip?

We already knew that Carrizo would support AVX2 (presumably with full 256-bit registers as well). We now know that the chip will add support for the BMI2, MOVBE, and RDRAND instructions as well. BMI2 refers to bit manipulation (manipulating code smaller than a word), RDRAND adds support for retrieving a random number from a hardware random number generator implemented on-die, and MOVBE is an Atom instruction (recently added to Haswell) that converts to and from little-endian to big-endian format. Nothing huge here, but it brings AMD up to parity with Haswell save for Intel’s TSX extensions.

BSN has the full details, but its article states that, while DDR3 and DDR4 are both implemented, there’s no word on DDR4 clock speeds and nothing on architectural enhancements save for a generic “architectural enhancements” prediction. That makes it difficult to predict exactly what’s in the pipe. The article makes no mention of GDDR5, which had previously provoked discussion after AMD’s Kaveri documentation indicated a GDDR5 controller was on-die. If AMD doesn’t bring a GDDR5 variant of Carrizo to market, it implies that the company will rely on dual DDR4 channels. That suggests a maximum bandwidth increase to 51.2GB/s, up from 38.4GB/s with DDR3-2400.

Considering that a 64-bit GDDR5 interface (Kaveri is implied to only have 2×32-bit GDDR5 channels on-die) would only offer a maximum bandwidth of 48-56GB/s, this suggests that AMD may simply wait a year for DDR4 to “catch up” rather than going to the trouble of attempting to launch a GDDR5 variant of its latest Steamroller chip — though this depends on DDR4-3200 actually being available at reasonable prices in 2015.

Major Southbridge changes — and some feature cuts

Carrizo will be AMD’s first APU to implement a full Fusion Control Hub (FCH) — what we used to call a “south bridge” — on-die, but it’s doing so at some cost to overall features. The FCH will be a stripped-down variant, with two SATA 6G ports, four USB 3.0 ports, and four USB 2.0 ports. This will only apply to mobile variants — drop a Carrizo APU into the FM2+ socket, and the onboard FCH will disable itself while the motherboard FCH takes over.

Up until now, all AMD’s southbridges have been built on 65nm. Bringing the FCH on-die means that Carrizo will save a few precious watts for mobile form factors in that fashion, while slashing the total feature size cuts die size and power consumption without boosting the APU’s physical area much.

Kaveri APU die shot. The large orange block is the GPU, and the two square green blocks are Steamroller cores.

The one potential downside, if this current version of the document is accurate, is that AMD is sharply cutting the number of available PCI-Express lanes. Carrizo increases all of its general purpose lanes to PCI-Express throughput, but it cuts the number of total lanes to 16, down from 24. For those of you following along at home, that means Carrizo motherboards will be limited to a single PCI-Express x8 lane for graphics, or two lanes that are electrically x4. There won’t be any simple way for a company to dodge that limit — not without implementing every other feature over alternate busses and dedicating the PCI-Express lanes solely to graphics.

If that actually happens, it could hurt AMD’s status in the enthusiast community if the news isn’t managed right. The truth is, a single PCIe 3.0 lane at x8 is likely enough for any single GPU — it’s only in multi-GPU configurations that such a configuration is likely to hurt. Here, AMD may simply be pragmatic — not many of its APU users are likely opting for multi-GPU configurations anyway. Depending on the clock speeds and performance advantages Carrizo can hit, it simply may not make sense for Kaveri owners or FX users to consider the chip as an upgrade, while the low-power Steam Machines of the world would be perfectly happy on an x8 slot.

There are a variety of other improvements to the server side, but these are the major points. Absent more information on the GPU or CPU IPC tweaks, it’s impossible to say for certain what AMD is targeting with this chip, but my gut says Carrizo is going to continue Kaveri’s plan of targeting performance-per-watt over raw performance. The chip is also expected to deploy HDLs (High Density Libraries) to boost the CPU’s density and reduce its die size — but it’s also expected to pay a frequency penalty for doing so.